A phase locked loop (PLL) is widely used for frequency synthesis. This type of looped system can multiply a reference frequency by an integer number and thus address an entire frequency range at a certain frequency step. More precisely, a phase locked loop is a servo-control system generating a frequency N times greater than the reference frequency that it receives in input, where N is an integer number. Thus, the output frequency given by a voltage-controlled oscillator is divided by N, and is then compared with a reference that may be supplied by a quartz. A charge pump formed from two current sources then reacts by injecting current into or drawing current out of the integrator filter that controls the output oscillator.
If the oscillator output frequency is an increasing function of its input voltage, the loop reaction is based on the following principle. The front comparator detects the first of the two fronts or leading edges. If this detected front belongs to the reference signal, the charge pump receives the command to send the current into the integrator filter. In this case, the output signal divided by N is delayed from the reference signal, and therefore the voltage at the oscillator terminals has to be increased.
Conversely, if the first detected front is the front of the output signal divided by N, the charge pump absorbs the current so that the voltage at the oscillator terminals drop. When the second front appears, the charge pump stops its activity while waiting for the next front. Thus, as the fronts become closer, the injected charge will be lower until the frequency of the oscillator output signal converges towards N times the reference frequency.
The phase locked loops can be used to synthesize frequencies with high precision and good stability. Their limitation is due to the fact that it is only possible to synthesize multiple integers, which limits the number of frequencies that can be addressed from a single reference frequency.
In order to overcome the problem of non-integer division, a “fractional” phase locked loop can be used that performs a succession of divisions by N and N+1. Thus, to make a division by N+0.5, we will divide once by N, then by N+1, and so on. The loop integrator filter then averages the value of the voltage controlling the loop output oscillator.
This type of architecture is one approach for dividing with a decimal part, but it introduces severe noise problems. Unlike the conventional phase locked loops mentioned above in which current injections are reduced until they become negligible under steady state conditions, fractional phase locked loops require large current injections at all times during their operation, since the frequency is between N and N+1 times the reference frequency, and it can only be compared at integer divisions.
These repeated current injections create noise that must be distributed. The size of the binary sequence controlling the divider by N or N+1 will impose this distribution. When the sequence is minimum, the oscillator voltage is modulated at the communication frequency of the dividers by N and N+1. The loop output spectrum then comprises two parasitic spikes. These spikes may cause major problems if they do respect noise specifications around the fundamental.
Furthermore, when the sequence becomes larger, parasite spikes due to the period of the sequence tend to spread. However, the loop integrator filter then has the time to react, which results in a variation of the fundamental with time. Thus, for very long sequences, parasitic spikes can be treated like noise distributed around the generated frequency, as a result of unwanted modulation of the output frequency.
In conclusion, the stability of the output frequency and the noise minimum very much limit the use of fractional phase locked loops.